UNL-DripGame Mapper Specification ------------ Introduction ------------ The NES port of Art Skiles's "Drip" has been assigned to the UNIF board name "UNL-DripGame". No iNES mapper number will be allocated. -------- Overview -------- This mapper supports one swappable 16KB PRG ROM bank (with a maximum of 256KB), four swappable 2KB CHR ROM banks (with a maximum of 32KB), vertical/horizontal/ single-screen (0 or 1) mirroring, MMC5-style attribute table expansion for each nametable, and two 8-bit PCM sound channels having 4-bit volume, 12-bit frequency, and 256-byte FIFO buffers to contain the sample data. This mapper is implemented on an FPGA, initialized from a serial EEPROM during powerup. --------- Registers --------- Readable registers: 4800 - [DSSS SSSS] - Misc Status D - DIP switch position (selects language) S: FPGA status - will return '110 0100' (ASCII 'd') when ready 5000 - [FE-- ----] - Sound Channel 0 Status 5800 - [FE-- ----] - Sound Channel 1 Status F - Indicates that FIFO is full E - Indicates that FIFO is empty Writable registers: 8000 - [---- ----] - Sound Channel 0 Clear FIFO 8004 - [---- ----] - Sound Channel 1 Clear FIFO Writing any value will silence the corresponding sound channel. 8001 - [dddd dddd] - Sound Channel 0 Data Port 8005 - [dddd dddd] - Sound Channel 1 Data Port Writing a value will insert it into the FIFO. 8002 - [pppp pppp] - Sound Channel 0 Period Low 8003 - [vvvv pppp] - Sound Channel 0 Period High + Volume 8006 - [pppp pppp] - Sound Channel 1 Period Low 8007 - [vvvv pppp] - Sound Channel 1 Period High + Volume p - Specifies channel playback rate, in cycles per sample v - Specifies channel playback volume 8008 - [iiii iiii] - IRQ Counter Low i - Specifies lower 8 bits of IRQ counter 8009 - [eiii iiii] - IRQ Counter High + Enable i - Specifies upper 7 bits of IRQ counter and resets timer e - Enable IRQ counter - on overflow, the counter is disabled. 800A - [---- SAMM] - Misc Control MM: Selects mirroring 00 - Vertical 01 - Horizontal 10 - 1-screen L 11 - 1-screen H A - Enable extended attribute table usage S - Allow writes to SRAM 800B - [---- PPPP] - PRG Select P - Select a 16KB PRG ROM page at CPU $8000-$BFFF 800C - [---- CCCC] - CHR Select 0 800D - [---- CCCC] - CHR Select 1 800E - [---- CCCC] - CHR Select 2 800F - [---- CCCC] - CHR Select 3 C - Select a 2KB CHR ROM page at PPU $0000-$07FF, $0800-$0FFF, $1000-$17FF, or $1800-$1FFF. C000-C3FF - [---- --AA] - Attribute Table 0 C400-C7FF - [---- --AA] - Attribute Table 1 A - Specify attribute data for the corresponding address within each nametable. ----- Notes ----- Readable I/O registers respond only to A11-A15 - that is, each register occupies a 2KB memory region (e.g. 4800-4FFF, 5000-57FF, 5800-5FFF) Writable registers 8000-800F are mirrored throughout 8000-BFFF (e.g. 8000 is mirrored at 8010/8020/.../BFF0, 8001 at 8011/8021/.../BFF1, etc.) Attribute expansion memory at C000-C7FF is mirrored throughout C000-FFFF. Data written to the IRQ Counter Low register is buffered until writing to IRQ Counter High, at which point the composite data is written directly to the IRQ timer. While the IRQ counter is enabled, the timer is decremented once per CPU cycle. Once the timer reaches zero, the /IRQ line is set to logic 0 and the timer stops decrementing - writing to the IRQ Enable register will acknowledge the interrupt and return the /IRQ signal to logic 1. Each sound channel maintains an internal timer and position register. When a channel's Clear FIFO register is written to, its timer is reset to the last written frequency and it is silenced. When data is written to an empty channel's Data Port, the channel's timer is reloaded from the Period registers and playback begins immediately. Each time the timer reaches zero, it is reloaded and a sample byte is fetched from the channel's FIFO. Sample values are biased by -0x80 and then multiplied by the channel's configured volume. If no value can be removed from the FIFO, the channel is silenced. Updates to a channel's Period do not take effect until the current sample has finished playing, but updates to a channel's Volume take effect immediately. As the mapper logic is loaded into an FPGA from a serial EEPROM, its functionality may not be available immediately after reset - games can detect mapper initialization by reading memory location $4800 and checking the lower 7 bits for the value 0x64 (ASCII 'd'). Mapper startup state is indeterminate. Last updated: 2006/08/22