Chip Images
by Quietust
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This page serves as a repository for chip images I have traced and analyzed.

If you'd like to contact me, email quietust at either or I can also be found in the #nesdev IRC channel on EFnet.

Active Projects: None


All - Recent - 2022 - 2020 - 2019 - 2015 - 2013 - 2012 - 2011

June 6, 2013

Over the past several months, numerous improvements have been made to the Visual 2C02, the latest of which involved a low-level change to the simulator itself - in particular, determining node values now considers the surface area of each node in the group to decide whether floating charges should propagate outwards or be drained away.

What Exactly Are These?

All chip images posted below are divided into several different layers. For ideal analysis, all of the images should be loaded as separate layers within a single master image using your graphics editor of choice, preferably making the Metal and Polysilicon layers partially transparent.

The layer descriptions below currently apply only to the chip images currently posted here, which all use depletion-load NMOS logic.

Not an actual layer on the chip, this simply serves to assign names to various signals for reference purposes.
Not an actual layer on the chip, this serves to group together certain parts of the chip according to their functionality for reference purposes.
This layer serves to connect different parts of the chip together, though older chips also use them to form the gates of transistors (instead of polysilicon). Newer chips often use multiple metal layers in order to save space.
In my images, red-colored metal is connected to VCC (+5V), green-colored metal is connected to GND (ground), and blue-colored metal forms interconnects.
Much like those found on printed circuit boards, vias form connections between layers. In this case, they connect the Metal layer to the Polysilicon and Diffusion layers.
In my images, vias are black.
When a Polysilicon trace passes directly between and thus connects two Diffusion regions, it forms the gate of a transistor. Polysilicon can also be used to form wires which connect sections of the chip to each other, mainly to route Metal interconnects underneath each other. In some cases, polysilicon can also be used to form capacitors and resistors.
In my images, polysilicon traces are purple.
Buried Contacts
Buried Contacts are just like Vias, except they cover larger areas and are used to form direct connections between Polysilicon and Diffusion without making transistors, thus avoiding the need to jump through Vias to the Metal layer and back.
In my images, buried contacts are light pink.
Transistors are one of the elementary components of electronics. Each transistor has 3 terminals - source, gate, and drain. The voltage applied to the gate determines the amount of resistance between the source and drain - low voltage results in high resistance (an open switch, "off"), and high voltage results in low resistance (a closed switch, "on"). The source and drain terminals of transistors are formed from the Diffusion layer, while the gate is usually made of polysilicon (though some older chips use metal gates). In depletion-load NMOS logic, certain transistors are depletion-mode - on by default, and generally used as pull-up resistors. Some chips also use depletion-mode transistors for design simplification (by allowing polysilicon to cross diffusion without forming transistors) or even to thwart reverse-engineering attempts (by creating fake transistors which don't actually do anything).
In my images, transistors are cyan.
Diffusion consists of conductive areas of silicon. Used alone, they can be used to form short interconnects or resistors, but their main purpose is to be used in pairs (along with Polysilicon traces running directly between them) to form the source and drain terminals of transistors. In some cases, diffusion can also be used to form capacitors and resistors.
In my images, red-colored diffusion is connected to VCC (+5V), green-colored diffusion is connected to GND (ground), and yellow-colored diffusion floats to whatever voltage is applied to it.

Each image is also timestamped in the tables below - since I trace the individual layers manually (as opposed to using sophisticated image analysis tools), I occasionally upload new versions whenever I find errors.


Status: Simulation

The RP2A03 is the NTSC version of the NES CPU; this particular chip is revision G. It contains 5 sound channels and a slightly modified (to remove decimal mode) MOS 6502. The 6502 itself is not included in the following layer images, mainly due to its complexity (and the fact that the Visual6502 project has already traced a real 6502).

The lack of decimal mode was seemingly intentional - 5 transistors (t1329, t2202, t2556, t2750, and t3212) were removed with surgical precision (one of which resulted in a strange "via to nowhere" observed at the very center of the following 2 images: 1, 2), the result being that the 6502's ALU no longer operates in decimal mode when the status register flag is set.

The Diffusion layer image is not 100% correct, as it was traced using the assumption that all intersections with Polysilicon formed enhancement-mode transistors (excluding the depletion-mode transistors which form pull-up resistors recognizeable both visually and programmatically). This assumption has already been proven false by the barrel shifters and full adders used in the frequency sweep logic for the 2 square wave channels - the layer image was updated to take this into account, but other similar instances may yet be lurking within the chip.

Using several special tools (and the Visual 6502 chip simulator and data), these layer images have been successfully combined to form The Visual 2A03.

Using the experience I've gathered from tracing this RP2A03, I'd eventually like to trace another one with the 6502 included, though I'll only do it if I can get better quality photographs (higher resolution, cleaner, and better focus), ideally from a fresh chip.

Errors found and fixed since making the simulator:

Known issues:

Interesting bus names to monitor (using "Trace these too"):

Last UpdatedSizeLayer
Sat, 07 May 2011 03:13:35 +000025,993 bytesLabels
Wed, 08 Jun 2011 00:27:13 +000070,564 bytesRegions
Thu, 23 Jun 2011 19:51:18 +000078,070 bytesMetal
Tue, 05 May 2020 23:41:54 +000064,764 bytesVias
Sat, 25 Jun 2011 00:39:15 +0000122,666 bytesPolysilicon
Fri, 24 Jun 2011 03:45:42 +000036,056 bytesBuried Contacts
Tue, 05 May 2020 18:39:38 +000054,567 bytesTransistors
Wed, 27 Jul 2011 02:45:46 +0000147,997 bytesDiffusion


Status: Simulation

The RP2C02 is the NTSC version of the NES PPU. Much of its behavior has been determined via "black box" reverse engineering, but the actual implementation of said functionality remains unknown.

The NESdev community donated several of these chips to the Visual6502 project, and several were depackaged, delayered, and photographed in order to produce the layer images below.

Several minor tweaks need to be made to these layer images for proper simulation:

Take a look at nodenames.js for a complete list of all interesting signals to use in "Trace these too" - as with the Visual 2A03, you can specify either individual nodes or entire buses (by omitting the number from the end).

The chip simulator currently resets at the very beginning of the pre-render scanline; otherwise, writes to certain registers would have no effect until after simulating an entire frame (which takes over 30 minutes).

Last UpdatedSizeLayer
Thu, 11 Aug 2011 01:36:00 +000028,519 bytesLabels
Sat, 14 Jul 2012 16:55:28 +000072,132 bytesRegions
Sun, 14 Aug 2011 03:27:00 +0000144,338 bytesMetal
Sun, 18 Nov 2012 03:11:25 +000097,053 bytesVias
Wed, 19 Jun 2013 22:37:43 +0000222,712 bytesPolysilicon
Tue, 26 Mar 2013 00:36:29 +000043,213 bytesBuried Contacts
Tue, 26 Mar 2013 00:35:25 +0000126,370 bytesTransistors
Wed, 31 Oct 2012 19:00:41 +0000138,517 bytesDiffusion


Status: Future

The RP2A07 is the PAL version of the NES CPU. The only known differences from the RP2A03 are the clock divider (divide by 16 instead of divide by 12) and several timer lookup values (noise, DPCM, and the frame timer).

No die shots of this chip are yet available.

The Visual6502 project claims to have one of these chips depackaged, but no plans to delayer or photograph it have been announced.


Status: Future

The RP2C07 is the PAL version of the NES PPU. The only known differences from the RP2C02 are the number of scanlines per frame, various timing details, and a different means of producing the video signal.

The Visual6502 project claims to have one of these chips depackaged and photographed, but no images have been made available.


Status: Abandoned

The 68000 is a CPU designed by Motorola, used in numerous computers including the classic Apple Macintosh and the Commodore Amiga. See Wikipedia for more information.

The layer image below was traced directly from the 10000x11299 die shots available here.

Olivier Galibert was able to produce a full transistor-level schematic of the 68000, partially assisted by this metal layer image (and some corrections).

Last UpdatedSizeLayer
Wed, 28 Sep 2011 00:14:06 +0000291,949 bytesMetal


Status: Stalled

The RP2C33 is the control chip used in Nintendo's Famicom Disk System, and it is responsible for controlling the disk drive, managing interrupts, and even playing sound.

The layer image below was traced from die shots acquired from Siliconpr0n, but it is not known whether it will ever be delayered.

Last UpdatedSizeLayer
Sun, 15 Feb 2015 18:42:42 +000063,357 bytesLabels
Mon, 22 Aug 2022 01:01:47 +0000282,750 bytesMetal
Mon, 22 Aug 2022 01:24:30 +0000121,275 bytesVias


Status: Simulation

The Konami VRC-VII is a support chip used in two Famicom game cartridges: Tiny Toon Adventures 2 and Lagrange Point.

The latter is best known for making use of the chip's expansion sound capabilities, which consists of 6-channel FM synthesis.

The chip also provides support for PRG and CHR bank switching, as well as a scanline-based interrupt counter.

The layer image below was traced from die shots acquired from Siliconpr0n, but it is not known whether it will ever be delayered.

ScottySR (who goes by the name "SCSR" on the NESdev Discord server) also independently traced all of the chip's layers (from the same source image I used); with those images (and some corrections), I was able to produce a visual chip simulator.

Last UpdatedSizeLayer
Fri, 19 Feb 2021 02:17:34 +000047,297 bytesLabels
Fri, 19 Feb 2021 02:16:26 +000082,770 bytesRegions
Fri, 19 Feb 2021 02:26:08 +0000321,268 bytesMetal
Fri, 19 Feb 2021 02:25:17 +0000125,796 bytesVias


Head over to my chipsim-tools GitHub repository for the tools I used to make the Visual 2A03. They may not be fully versatile and efficient, but they get the job done.


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